Testing systems that test electrical characteristics of integrated circuits are known. The testing systems typically provide electrical power and a test sequence of user inputs to the integrated circuit for testing. The testing systems also provide scan data to the integrated circuit for testing. The scan data is typically provided to a non-user input (test input) that is used during testing. The scan data presets internal states of the integrated circuit at a start of testing sequence.
Existing testing systems include a limited amount of memory that can be addressed for storing scan data. As the number of function block designs in an integrated circuit increases with increasingly complex integrated circuits, integrated circuit designers have turned to acquisition of selected function block designs from third party vendors of such function block designs. Each of these function block designs includes a set of scan data for the function block. The length of the scan data sequence is typically large. A custom set of scan data is also developed for a custom portion of the integrated circuit. In many cases of complex integrated circuits, the aggregate amount of scan data for a single function block exceeds the size of the limited amount of memory in an existing testing system. Compression of scan data is known. However, even with compression of scan data, the size of the tester memory is exceeded by compressed scan data.
A method and apparatus are needed to enable use of existing integrated circuit testers with integrated circuits that have function blocks with scan data sizes that exceed a memory size of the integrated circuit tester.